Benelux Heterogeneous Integration Conference 2026

Eric Beyne (Imec)

The future of electronic systems: 3D heterogenous partitioning and technology, from multi-chip modules to CMOS 2.0

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High-performance electronic systems have always been a main driver for technology development. Today, artificial intelligence systems benefit from increased circuit integration and a high degree of interconnectivity, in particular high-bandwidth memory connections. Although logic circuit integration continues to scale in density, different technologies are needed for memory and logic. Rather than monolithic integration, 3D-SOC aims to realize the circuit using different circuit technologies, stacking the layers with fine-pitch interconnects. As we go deeper in the circuit system hierarchy, exponentially increasing 3D interconnect pitches are required. Hybrid bonding is recognized as the key technology for advanced heterogeneous wafer-level system integration. This is enabled through aggressive pad size and 3D interconnect pitch scaling, resulting in minimal electrical die-to-die interconnect delay. Another key technology is backside power delivery and backside connectivity, enabled by extreme wafer thinning and nTSV integration. This enables the stacking of multiple front-end device layers, connecting at the front and bottom sides with fine interconnect pitches. We call this dense 3D stacking of device layers CMOS 2.0.

Eric Beyne obtained an MSc degree in electrical engineering in 1983 and a PhD in applied sciences in 1990, both from KU Leuven, Belgium. Since 1986, he’s been with Imec in Leuven. Currently, he’s Imec senior fellow, VP R&D and director of Imec’s 3D System Integration program, in which Imec’s own staff works alongside engineers from 50+ industrial partners (IDMs, foundries, fabless semiconductor companies, OSATs, as well as equipment, material and software tool suppliers).

Vishal Saroha (Yole Group)

Heterogeneous integration at scale: the equipment race shaping the next semiconductor era

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Heterogeneous integration is moving from advanced packaging buzzword to a manufacturing reality that reshapes how the semiconductor industry invests, collaborates and competes. While much attention is placed on architectures and materials, the real enabler sits on the factory floor. Equipment is becoming the critical bottleneck and the main differentiator.
This talk explores how wafer front-end, assembly and test equipment are adapting to new integration schemes such as hybrid bonding, advanced interconnects and chiplet-based architectures to support high interconnect density, tighter process control and higher throughput for heterogeneous integration. It will highlight where existing tools are being stretched beyond their original design intent and where new platforms are emerging across bonding, patterning, metrology & inspection and test.
Beyond technology, the talk will address market dynamics and supply chain implications. Equipment suppliers, subsystem providers and engineering service companies play an increasingly strategic role, particularly in regions like Europe and Asia, where co-development is essential. Understanding these shifts is key to scaling heterogeneous integration from pilot lines to high-volume manufacturing.

Vishal Saroha is a technology & market analyst at Yole Group, where he focuses on market intelligence and consulting activities on semiconductor equipment, manufacturing and the global supply chain. Prior to Yole, he worked at GlobalFoundries in Dresden as a senior integration engineer, driving device and SRAM optimization for their 22FDX technology platform. Before that, he was at Imec in Belgium, where he worked on 3D IC integration and device reliability. He holds a master’s degree in nanotechnology from KU Leuven and a bachelor’s degree in physics from the University of Delhi.

James Robinson (Infinitesima)

Angstroms to millimeters: holistic surface characterization for 3D integration via hybrid optical AFM metrology

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As hybrid bonding scales toward sub-micron pitches, the industry faces a critical metrology ‘blind spot’: the need to simultaneously capture sub-nanometer roughness and millimeter-scale wafer flatness without sacrificing HVM (high-volume manufacturing) throughput. While atomic force microscopy (AFM) has long been the gold standard for resolution, its historic speed constraints have relegated it to R&D labs.
This talk introduces a paradigm shift in in-line process control via the Metron3D solution. It utilizes a hybrid optical AFM system, the Rapid Probe Microscope (RPM), which, combined with a high-speed wafer stage and surface detection, enables dense sampling across entire 300 mm wafers at speeds compatible with mass production. We demonstrate that a single high-speed AFM system can provide a comprehensive flatness profile – from local copper dishing and dielectric roughness to macro-scale topography at sub-nanometer precision. Data from a 3D integration development partner will be presented, proving that Metron3D delivers the multi-scale data density required to ensure high-yield bonding interfaces in advanced semiconductor manufacturing.

James Robinson received an MEng in material science from Oxford University and moved directly to industry as a research engineer developing plasma deposition processes. He transitioned to commercial roles early in his career and spent three years as a product manager at Oxford Instruments before joining Infinitesima in 2022. As product marketing director, he manages the interface between the development teams and the customers.

Martijn Heck (Eindhoven University of Technology)

Integrated photonics and electronics – a forced marriage?

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Optical communications increasingly replaces traditional copper lines in our communication systems. This started decades ago with long haul communications, across oceans and countries, and now fiber-to-the-home and optics in data centers are commonplace. This is driven by an exponential increase in demand for bandwidth, bandwidth density and energy efficiency. Photonic integration, or optical chips, is often used to build the transceivers in such systems. Driven by, among other things, AI demands, the next logical step will be that chips will communicate optically, between processors and memory, for example. This requires the optics to be co-packaged or even heterogeneously integrated, using chiplets, with the electronic chips. This talk will discuss the opportunities and challenges, most notably how the photonics community will need to start thinking like the electronics community and how the electronics community will have to start embracing a level of heterogeneity where photonics will be an integral part of chip design.

Martijn Heck has a PhD in electrical engineering from Eindhoven University of Technology, where he has been a full professor since 2020. He was scientific director of the Eindhoven Hendrik Casimir Institute and co-founded the Casimir Institute for Future Chips. Previously, he was a postdoctoral researcher at the Free University of Amsterdam (2008-2009) and the University of California, Santa Barbara, US (2009-2013), and an associate professor at Aarhus University, Denmark (2013-2020). His research focuses on photonic integration, from technology development, including heterogeneous integration techniques, to applications in sensors, microwave and terahertz photonics, quantum technology and interconnects.

Gerwin Gelinck (TNO/PITC/University of Twente)

When lasers build chips: a new path to photonic chip assembly

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Current pick‑and‑place and bonding techniques don’t offer the precision, speed or cost efficiency needed for next‑generation co‑packaged optics and advanced photonic designs. In this talk, we introduce a new die‑to‑wafer assembly method that uses high‑throughput laser-induced forward transfer (LIFT). LIFT is a non‑contact, laser‑based printing process that transfers (photonic) components from a donor wafer to a target wafer quickly and with very high placement accuracy. With the ability to reach sub‑micrometer – and ultimately below 200 nm – alignment at high speed (> 10,000 components per hour), this method changes what’s technically and economically possible. The process works with many material types – we’ll show examples including III‑V photonic chips, micro‑LEDs and ultra‑thin optical lenses. We believe that LIFT offers a strong platform for next‑generation heterogeneous photonic integration and opens the door to true 2.5D and 3D stacking for dense, low‑power optical interconnects.

Gerwin Gelinck is program manager heterogeneous integration at TNO’s Photonic Integration Technology Center (PITC) and professor of integrated photonics at the University of Twente. His academic and industrial journey has consistently revolved around the development and application of novel electronic and photonic materials, with a strong emphasis on thin-film technologies and device integration. This foundation is highly relevant to the field of integrated photonics, which increasingly relies on heterogeneous material systems, advanced packaging and scalable manufacturing techniques to meet the demands of next-generation applications.

André van Geelen (Coolsem)

Redefining chip cooling for next-generation heterogeneous platforms

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As heterogeneous integration combines III-V and photonic with RF or power devices into increasingly compact systems, thermal bottlenecks are becoming the primary limiter of performance, reliability and efficiency. Coolsem introduces a wafer-level thermal integration approach that fundamentally redefines chip cooling by removing the substrate and replacing it with a proprietary composite stack. This wafer-level thermal interface stack (Waltis) delivers an ultra-low thermal resistance, offering up to 15 times better thermal management and 25–55 °C lower chip temperatures, boosting performance and reliability while reducing cooling energy by 50 percent. By dramatically reducing temperature gradients between active devices and their thermal foundation, the technology enables higher output power, improved efficiency and extended lifetime across RF, photonic and power applications. This talk will outline the integration concept, material stack design, thermo-mechanical considerations and application results, demonstrating how wafer-level thermal engineering becomes a scalable enabler for next-generation heterogeneous systems.

André van Geelen is a seasoned semiconductor and photonics executive with deep expertise in technology, business strategy and innovation. He began his career at industry leaders including Philips, JDS-Uniphase and NXP, and played a pivotal role in early high-tech ventures such as Threefive Photonics and Antenna Tuners. In 2007, he founded Epcos Netherlands via a spinout from NXP, which was later acquired by Qualcomm. Since 2015, he’s advised and supported high-tech startups and scale-ups on strategic direction, go-to-market execution and funding. As founder and CTO of Coolsem Technologies, he drives the development of wafer-level thermal management solutions that help semiconductor, RF, power and photonic devices run cooler, more reliably and with greater energy efficiency.

Kouchi Zhang (Delft University of Technology)

Enabling the “Electronics Cambrian Explosion” by heterogeneous system integration and packaging

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Heterogenous system integration and packaging have always been essential parts of the global semiconductor value chain. However, they were not considered as technologically challenging and scientifically exciting as the front-end chip technology. Today, with the semiconductor industry in transition toward system-technology co-optimization, AI-assisted design and vertically integrated chiplet ecosystems, the critical bottleneck is shifting from transistor scaling only to heterogeneous system integration, and the semiconductor system architecture is in redefinition. This talk will highlight some application-driven packaging technology roadmaps and the underlying scientific challenges. Some EU and NL perspectives will also be discussed.

G.Q. (Kouchi) Zhang is an IEEE Fellow for heterogeneous system integration and reliability, and chair professor at Delft University of Technology. His research focuses on multi-level heterogeneous system integration and advanced packaging, multi-physics and multiscale modeling and optimization, digital twins for reliability and wide-bandgap semiconductor sensors and components. He’s a recipient of the IEEE Technical Field Award in Electronic Packaging and the IEEE CPMT Sustained Technical Achievement Award. He chaired “More than Moore” of the European Nanoelectronics Initiative Advisory Council (ENIAC) and co-chaired the Academic Council of the Dutch national innovation program “Micro/Nanoelectronics and Embedded Systems” (Point-One), leading talent development and academia–industry collaboration. He initiated MEMSLand, the largest Dutch public–private MEMS/sensor innovation program prior to the Top Sectors initiative, and was a co-founder of the Chip Integration Technology Center (CITC) in Nijmegen.

Joep Stokkermans (Itec Equipment)

Driving advanced packaging from core competence to core business

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Advanced packaging technologies can be effectively applied in the high-volume production of semiconductors like discrete power transistors. These products perform better, have lower material cost and are made in an environmentally sustainable way. Today, panel-level back-end processes exist that, at the same production volume, can outperform existing back-ends that produce on leadframes. These wafer-level or panel-level processes can reduce or even eliminate complexity in the semiconductor back-end. This talk will present a vision on how the Netherlands can use its core technology to become and stay leading in advanced packaging products and equipment.

Joep Stokkermans holds an MSc in precision and microsystems engineering from Delft University of Technology. In the TUD Extreme Assembly Laboratory, he’s still actively researching advanced technologies for microchip assembly. As the innovation director of Itec, he’s responsible for Itec Ventures, which is driving the next generation of chip assembly and test equipment, as well as related smart IT solutions. He has also co-founded TNO’s Chip Integration Technology Center and has vast experience in realizing systematic innovations in semiconductor back-end manufacturing.

22 May 2026 | Mikrocentrum Veldhoven

22 May 2026

Mikrocentrum Veldhoven

Exhibition and conference on advanced semiconductor systems development in the Low Countries, bringing together the semiconductor, optical communication, photonics and equipment communities focusing on advanced packaging

Exhibition and conference on advanced semiconductor systems development in the Low Countries

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Program

Confirmed speakers

09:30-09:45

Registration

09:45-10:30

Keynote

The future of electronic systems: 3D heterogenous partitioning and technology, from multi-chip modules to CMOS 2.0

Eric Beyne (Imec)

10:30-11:00

Break

11:00-11:30

Enabling the “Electronics Cambrian Explosion” by heterogeneous system integration and packaging

Kouchi Zhang (Delft University of Technology)

11:30-12:00

Redefining chip cooling for next-generation heterogeneous platforms

André van Geelen (Coolsem)

12:00-13:30

Lunch

13:30-14:00

Driving advanced packaging from core competence to core business

Joep Stokkermans (Itec Equipment)

14:00-14:30

Angstroms to millimeters: holistic surface characterization for 3D integration via hybrid optical AFM metrology

James Robinson (Infinitesima)

14:30-15:00

Break

15:00-15:30

When lasers build chips: a new path to photonic chip assembly

Gerwin Gelinck (TNO/PITC/University of Twente)

15:30-16:00

Integrated photonics and electronics – a forced marriage?

Martijn Heck (Eindhoven University of Technology)

16:00-16:30

Break

16:30-17:15

Keynote

Heterogeneous integration at scale: the equipment race shaping the next semiconductor era

Vishal Saroha (Yole Group)

Drinks

About

Target audience

Location

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27 May 2026